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INTEGRATED CIRCUITS
DATA SHEET
TEA6322T Sound fader control circuit
Preliminary specification File under Integrated Circuits, IC01 1995 Dec 19
Philips Semiconductors
Preliminary specification
Sound fader control circuit
FEATURES * Source selector for three stereo and one differential stereo input for remote sources * The differential stereo input works optional as a fourth stereo input and the common mode pin can be used as well as an additional mono input * Interface for noise reduction circuits * Interface for external equalizer * Volume, balance and fader control * Output at volume I for external booster * Special loudness characteristic automatically controlled in combination with volume setting * Bass and treble control * Mute control at audio signal zero crossing * Logic output to read mute status * Fast mute control via I2C-bus * Fast mute control via pin * I2C-bus control for all functions * Power supply with internal power-on reset * Power-down indication. QUICK REFERENCE DATA SYMBOL VCC ICC Vo(rms) Gv Gstep(vol) Gbass Gtreble Gstep(treble) (S+N)/N RR100 CMRR PARAMETER supply voltage supply current maximum output voltage level voltage gain step resolution (volume) bass control treble control step resolution (bass, treble) signal-plus-noise to noise ratio VO = 2.0 V; Gv = 0 dB; unweighted ripple rejection common mode rejection ratio differential stereo input Vr(rms) < 200 mV; f = 100 Hz; Gv = 0 dB VCC = 8.5 V CONDITIONS - -86 - -15 -12 - - - 43 MIN. 7.5 VCC = 8.5 V; THD 0.1% - TYP. 8.5 26 2000 - 1 - - 1.5 105 75 53 GENERAL DESCRIPTION
TEA6322T
The sound fader control circuit TEA6322T is an I2C-bus controlled stereo preamplifier for car radio hi-fi sound applications.
MAX. 9.5 - - +20 - +15 +12 - - - - V
UNIT mA mV dB dB dB dB dB dB dB dB
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TEA6322T 1995 Dec 19 VSO40 DESCRIPTION plastic very small outline package; 40 leads 2 VERSION SOT158-1
2.2 k
handbook, full pagewidth
1995 Dec 19
8.2 nF 20 k CKVL 220 nF 100 F VCC 13 26 38 3 4 24 47 F 9 x 220 nF input left source input mono source 20 18 16 14 17 27 input right source CKIN 25 23 21 28 220 nF CKVL 8.2 nF 20 k 30 SOURCE SELECTOR POWER SUPPLY 11 GND
BLOCK DIAGRAM
Philips Semiconductors
Sound fader control circuit
OVL 2.2 k 33 nF 5.6 nF 150 nF 4.7 k MUTE 10 9 8 7 2 MUTE FUNCTION ZERO CROSS DETECTOR VOLUME I +20 to -31 dB LOUDNESS LEFT BASS LEFT 15 dB TREBLE LEFT 12 dB VOLUME II 0 to -55 dB BALANCE FADER REAR 5 +5V
12
output left VOLUME II 0 to -55 dB BALANCE FADER FRONT 6
40 LOGIC I2C-BUS RECEIVER 1
SCL SDA
3
VOLUME I +20 to -31 dB LOUDNESS RIGHT
BASS RIGHT 15 dB
TREBLE RIGHT 12 dB
VOLUME II 0 to -55 dB BALANCE FADER FRONT
35
output right VOLUME II 0 to -55 dB BALANCE FADER REAR 36
TEA6322T
29 31 32 33 34
MHA084
150 nF 5.6 nF 33 nF
Preliminary specification
TEA6322T
OVR
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Sound fader control circuit
PINNING SYMBOL SDA MUTE DGND AGND OUTLR OUTLF TL B2L B1L OVL IVL ILL QSL IDL i.c. ICL COM IBL i.c. IAL IAR i.c. IBR CAP ICR Vref IDR QSR ILR IVR OVR B1R B2R TR OUTRF OUTRR n.c. VCC n.c. SCL 1995 Dec 19 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 serial data input/output mute control input and output digital ground analog ground output left rear output left front treble control capacitor left channel or input from external equalizer bass control capacitor left channel or output to an external equalizer bass control capacitor, left channel output volume I, left channel input volume I, left control part input loudness, left control part output source selector, left channel input D left source COMM, common mode rejection adjust, centre position input C left source common mode input / mono source input input B left source COML, common mode rejection adjust, left position input A differential source left input A differential source right COMR, common mode rejection adjust, right position input B right source electronic filtering for supply input C right source reference voltage (0.5 VCC) input D right source output source selector right channel input loudness right channel input volume I, right control part output volume I, right channel bass control capacitor right channel bass control capacitor right channel or output to an external equalizer DESCRIPTION
TEA6322T
treble control capacitor right channel or input from an external equalizer output right front output right rear not connected supply voltage not connected serial clock input 4
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
The volume control function is split into two sections: volume I control block and volume II control block.
handbook, halfpage
SDA MUTE DGND AGND OUTLR OUTLF TL B2L B1L
1 2 3 4 5 6 7 8 9
40 SCL 39 n.c. 38 VCC 37 n.c. 36 OUTRR 35 OUTRF 34 TR 33 B2R 32 B1R 31 OVR
The control range of volume I is between +20 dB and -31 dB in steps of 1 dB. The volume II control range is between 0 dB and -55 dB in steps of 1 dB. Although the theoretical possible control range is 106 dB (+20 to -86 dB), in practice a range of 86 dB (+20 to -66 dB) is recommended. The gain/attenuation setting of the volume I control block is common for both channels. The volume I control block operates in combination with the loudness control. The filter is linear when the maximum gain for the volume I control (+20 dB) is selected. The filter characteristic increases automatically over a range of 32 dB down to a setting of -12 dB. That means the maximum filter characteristic is obtained at -12 dB setting of volume I. Further reduction of the volume does not further influence the filter characteristic (see Fig.5). The maximum selected filter characteristic is determined by external components. The proposed application gives a maximum boost of 17 dB for bass and 4.5 dB for treble. The loudness may be switched on or off via I2C-bus control (see Table 7). The volume I control block has an output pin and is followed by the bass control block. A single external capacitor of 33 nF for each channel in combination with internal resistors, provides the frequency response of the bass control (see Fig.3). The adjustable range is between -15 and +15 dB at 40 Hz. Both loudness and bass control result in a maximum bass boost of 32 dB for low volume settings. The treble control block offers a control range between -12 and +12 dB in steps of 1.5 dB at 15 kHz. The filter characteristic is determined by a single capacitor of 5.6 nF for each channel in combination with internal resistors (see Fig.4). The basic step width of bass and treble control is 3 dB. The intermediate steps are obtained by switching 1.5 dB boost and 1.5 dB attenuation steps. The bass and treble control functions can be switched off via I2C-bus. In this event the internal signal flow is disconnected. The connections B2L and B2R are outputs and TL and TR are inputs for inserting an external equalizer.
OVL 10
TEA6322T
IVL 11 ILL 12 QSL 13 IDL 14 i.c. 15 ICL 16 COM 17 IBL 18 i.c. 19 IAL 20
MHA085
30 IVR 29 ILR 28 QSR 27 IDR 26 Vref 25 ICR 24 CAP 23 IBR 22 i.c. 21 IAR
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION The source selector allows either the source selection between the differential stereo input (IAL, IAR and COM) and three stereo inputs, or selection of four stereo inputs and the mono input (COM). The maximum input signal voltage is Vi(rms) = 2 V. The outputs of the source selector and the inputs of the following volume control parts are available at pins 13 and 11 for the left channel and pins 28 and 30 for the right channel. This offers the possibility of interfacing a noise reduction system. The volume control part is following the source selector. The signal phase from input volume control part to all outputs is 180.
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
The last section of the circuit is the volume II block. The balance and fader functions are performed using the same control blocks. This is realized by 4 independently controllable attenuators, one for each output. The control range of these attenuators is 55 dB in steps of 1 dB with an additional mute step. The circuit provides 3 mute modes: 1. Zero crossing mode mute via I2C-bus using 2 independent zero crossing detectors (ZCM, see Tables 2 and 9). 2. Fast mute via MUTE pin. 3. Fast mute via I2C-bus either by general mute (GMU, see Tables 2 and 9) or volume II block setting (see Table 4). The mute function is performed immediately if ZCM is cleared (ZCM = 0). If the bit is set (ZCM = 1) the mute is activated after changing the GMU bit. The actual mute switching is delayed until the next zero crossing of the audio frequency signal. As the two audio channels (left and right) are independent, two comparators are built-in to control independent mute switches. To avoid a large delay of mute switching when very low frequencies are processed or the output signal amplitude is lower than the DC offset voltage a second I2C-bus transmission is needed. Both transmissions have the same data and the second transmission a delay time of e.g. 100 ms. The first transmission starts the zero cross circuit, but second transmission moves the mute switch immediately if the circuit has no zero cross detected.
TEA6322T
The mute function can also be controlled externally. If the mute pin is switched to ground all outputs are muted immediately (except the outputs volume left and right (OVL and OVR) and hardware mute). This mute request overwrites all mute controls via the I2C-bus for the time the pin is held LOW. The hardware mute position is not stored in the TEA6322T. The MUTE pin can also be used as output. The mute pin voltage is LOW when all outputs are in mute position. For the turn on/off behaviour the following explanation is generally valid. To avoid AF output caused by the input signal coming from preceding stages, which produces output during drop of VCC, the mute has to be set, before the VCC will drop. This can be achieved by I2C-bus control or by grounding the MUTE pin. For use where is no mute in the application before turn off, a supply voltage drop of more than 1 x VBE will result in a mute during the voltage drop. The power supply should include a VCC buffer capacitor, which provides a discharging time constant. If the input signal does not disappear after turn off the input will become audible after certain time. A 4.7 k resistor discharges the VCC buffer capacitor, because the internal current of the IC does not discharge it completely. The hardware mute function is favourable for use in Radio Data System (RDS) applications. The zero crossing mute avoids modulation plops. This feature is an advantage for mute during changing presets and/or sources (e.g. traffic announcement during cassette playback).
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC Vn Tamb Tstg Ves Note 1. Human body model: C = 100 pF; R = 1.5 k; V 2 kV. Charge device model: C = 200 pF; R = 0 ; V 500 V. PARAMETER supply voltage voltage at pins 1, 2 and 5 to 40 to pins 3 and 4 operating ambient temperature storage temperature electrostatic handling note 1 CONDITIONS 0 0 -40 -65 MIN. 10 VCC +85 +150 MAX. V V C C UNIT
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
CHARACTERISTICS VCC = 8.5 V; RS = 600 ; RL = 10 k; CL = 2.5 nF; AC coupled; f = 1 kHz; Tamb = 25 C; gain control Gv = 0 dB; bass linear; treble linear; fader off; balance in mid position; loudness off; unless otherwise specified. SYMBOL VCC ICC VDC Vref Gv(max) Vo(rms) PARAMETER supply voltage supply current internal DC voltage at inputs and outputs internal reference voltage at pin 26 maximum voltage gain output voltage level for Pmax at the power output stage start of clipping THD 0.5%; see Fig.10 THD = 1%; Gv = 3 dB RL = 2 k; CL = 10 nF; THD = 1% Vi(rms) fro input sensitivity roll-off frequency CKIN = 220 nF; CKVL = 220 nF; Zi = Zi(min) low frequency (-1 dB) low frequency (-3 dB) high frequency (-1 dB) CKIN = 470 nF; CKVL = 100 nF; Zi = Zi(typ) low frequency (-3 dB) cs THD channel separation total harmonic distortion Vi = 2 V; frequency range 250 Hz to 10 kHz frequency range 20 Hz to 12.5 kHz Vi = 100 mV; Gv = 20 dB - Vi = 1 V; Gv = 0 dB Vi = 2 V; Gv = 0 dB Vi = 2 V; Gv = -10 dB RR ripple rejection Vr(rms) < 200 mV f = 100 Hz f = 40 Hz to 12.5 kHz 70 - 76 66 - - dB dB - - - 0.1 0.05 0.1 0.1 - 0.1 - - % % % % 60 30 20000 17 - - - - - - - - Hz Hz Hz Hz - 2300 2000 2000 - - 200 - - - - mV mV mV mV RS = 0 ; RL = CONDITIONS - 3.83 - 19 MIN. 7.5 TYP. 8.5 26 4.25 4.25 20 MAX. 9.5 33 4.68 - 21 UNIT V mA V V dB
Vo = 2000 mV; Gv = 20 dB -
74
80
-
dB
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
SYMBOL (S+N)/N
PARAMETER signal-plus-noise to noise ratio
CONDITIONS unweighted; 20 Hz to 20 kHz (RMS); Vo = 2.0 V; see Figs 6 and 7 CCIR468-2 weighted; quasi peak; Vo = 2.0 V Gv = 0 dB Gv = 12 dB Gv = 20 dB differential input Gv = 0 dB Gv = 20 dB - - - - - -
MIN.
TYP. 105 -
MAX.
UNIT dB
95 88 81 90 79 53 -
- - - - - - 10
dB dB dB dB dB dB nW
CMRR Pno(rms)
common mode rejection ratio differential stereo input noise output power (RMS value) only contribution of TEA6322T; power amplifier for 6 W crosstalk V bus ( p - p ) 20 log -------------------------- between bus V o ( rms ) inputs and signal outputs mute position; note 1
43 -
ct
note 2
-
110
-
dB
Source selector Zi S Vi(rms) Voffset input impedance input isolation of one selected source to any other input maximum input voltage (RMS value) DC offset voltage at source selector output by selection of any stereo inputs by selection of differential input or mono input Zo RL CL Gv Zi Zo RL CL 1995 Dec 19 output impedance output load resistance output load capacity voltage gain, source selector - - - 10 0 - - - 80 - - 0 10 20 120 - 2500 - mV mV k pF dB f = 1 kHz f = 12.5 kHz THD < 0.5%; VCC = 8.5 V THD < 0.5%; VCC = 7.5 V 25 - - - - 35 105 95 2.15 1.8 45 - - - - k dB dB V V
Control part (source selector disconnected; source resistance 600 ) input impedance volume input input impedance loudness input output impedance output load resistance output load capacity 8 100 25 - 2 0 150 33 80 - - 200 40 120 - 10 k k k nF
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
SYMBOL Vi(rms) Vno
PARAMETER maximum input voltage (RMS value) noise output voltage
CONDITIONS THD < 0.5% CCIR468-2 weighted; quasi peak Gv = 20 dB Gv = 0 dB Gv = -66 dB mute position - - - - - - - - Gv = +20 to -50 dB Gv = -51 to -66 dB Gv = +20 to -50 dB see Fig.9 Gv = 0 to -66 dB Gv = 20 to 0 dB Gv = 0 to -66 dB Gv = 20 to 0 dB Gv = 0 to -31 dB; loudness on - - - -
MIN.
TYP. 2.15 -
MAX.
UNIT V
110 33 13 10 106 86 1 - - - - 110 0.2 2 - - -
220 50 22 - - - - 0.5 2 3 2 - 10 15 10 40 17
V V V V dB dB dB dB dB dB dB dB mV mV mV mV mV
CRtot Gstep
total continuous control range recommended control range step resolution step error between any adjoining step
Ga Gt MUTEatt Voffset
attenuator set error gain tracking error mute attenuation DC step offset between any adjoining step DC step offset between any step to mute
100 - - - - -
Volume I control and loudness CRvol Gv Gstep LBmax continuous volume control range voltage gain step resolution maximum loudness boost loudness on; referred to loudness off; boost is determined by external components f = 40 Hz f = 10 kHz Bass control Gbass Gstep bass control, maximum boost maximum attenuation step resolution (toggle switching) step error between any adjoining step Voffset DC step offset in any bass position f = 40 Hz f = 40 Hz f = 40 Hz f = 40 Hz 14 14 - - - 15 15 1.5 - - 16 16 - 0.5 20 dB dB dB dB mV - - 17 4.5 - - dB dB - -31 - 51 - 1 - +20 - dB dB dB
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
SYMBOL Treble control Gtreble
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
treble control, maximum boost maximum attenuation maximum boost
f = 15 kHz f = 15 kHz f > 15 kHz f = 15 kHz f = 15 kHz
11 11 - - - -
12 12 - 1.5 - -
13 13 15 - 0.5 10
dB dB dB dB dB mV
Gstep
step resolution (toggle switching) step error between any adjoining step
Voffset CR Gstep
DC step offset in any treble position
Volume II, balance and fader control continuous attenuation fader and volume control range step resolution attenuation set error Mute function VmuteLOWI VmuteLOWO VmuteHIGH VCCdrop input level for fast mute detection input level for no mute detection output level for mute pull-up voltage supply drop to VCAP for mute active I 1 mA; CL 100 pF open collector - 2.2 - - - - - - - -0.7 1.0 - 0.4 VCC - V V V V V 53.5 - - 55 1 - 56.5 2 1.5 dB dB dB
Power-on reset (when reset is active the GMU-bit (general mute) is set and the I2C-bus receiver is in reset position) VCC increasing supply voltage start of reset end of reset decreasing supply voltage start of reset Digital part (I2C-bus pins); note 3 ViH ViL IiH IiL VoL HIGH level input voltage LOW level input voltage HIGH level input current LOW level input current LOW level output voltage IL = 3 mA VCC = 0 to 9.5 V 3 -0.3 -10 -10 - - - - - - 9.5 +1.5 +10 +10 0.4 V V A A V - 5.2 4.2 - 6.5 5.5 2.5 7.2 6.2 V V V
Notes to the characteristics 1. The indicated values for output power assume a 6 W power amplifier at 4 with 20 dB gain and a fixed attenuator of 12 dB in front of it. Signal-to-noise ratios exclude noise contribution of the power amplifier. 2. The transmission contains: total initialization with MAD and subaddress for volume and 8 data words, see also definition of characteristics, clock frequency = 50 kHz, repetition burst rate = 400 Hz, maximum bus signal amplitude = 5 V (p-p). 3. The AC characteristics are in accordance with the I2C-bus specification. This specification, "The I2C-bus and how to use it", can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
I2C-BUS PROTOCOL I2C-bus format S(1) Notes 1. S = START condition. 2. SLAVE ADDRESS (MAD) = 1000 0000. 3. A = acknowledge, generated by the slave. 4. SUBADDRESS (SAD), see Table 1. SLAVE ADDRESS(2) A(3) SUBADDRESS(4) A(3) DATA(5)
TEA6322T
A(3)
P(6)
5. DATA, see Table 1; if more than 1 byte of DATA is transmitted, then auto-increment of the significant subaddress is performed. 6. P = STOP condition. Table 1 Second byte after MAD MSB FUNCTION Volume/loudness Fader front right Fader front left Fader rear right Fader rear left Bass Treble Switch Note 1. Significant subaddress. V FFR FFL FRR FRL BA TR S BIT 7 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 2(1) 0 0 0 0 1 1 1 1 1(1) 0 0 1 1 0 0 1 1 LSB 0(1) 0 1 0 1 0 1 0 1
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 2 Definition of third byte after MAD and SAD MSB FUNCTION Volume/loudness Fader front right Fader front left Fader rear right Fader rear left Bass Treble Switch Notes 1. Zero crossing mode. 2. Switch loudness on/off. 3. Volume control. 4. Don't care bits (logic 1 during testing). 5. Fader control front right. 6. Fader control front left. 7. Fader control rear right. 8. Fader control rear left. 9. Bass control. 10. Treble control. 11. Mute control for all outputs except OVL and OVR (general mute). 12. Source selector control. V FFR FFL FRR FRL BA TR S BIT 7 ZCM(1) 0 0 0 0 0 0 GMU(11) 6 LOFF(2) 0 0 0 0 0 0 0 5 V5(3) FFR5(5) FFL5(6) FRR5(7) FRL5(8) 0 0 0 4 V4(3) FFR4(5) FFL4(6) FRR4(7) FRL4(8) BA4(9) TR4(10) 0 3 V3(3) FFR3(5) FFL3(6) FRR3(7) FRL3(8) BA3(9) TR3(10) 0 2 V2(3) FFR2(5) FFL2(6) FRR2(7) FRL2(8) BA2(9) TR2(10) SC2(12)
TEA6322T
LSB 1 V1(3) FFR1(5) FFL1(6) FRR1(7) FRL1(8) BA1(9) TR1(10) SC1(12) 0 V0(3) FFR0(5) FFL0(6) FRR0(7) FRL0(8) BA0(9) TR0(10) SC0(12)
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 3 Volume I setting Gv (dB) DATA V5 V4 V3 V2 V1
TEA6322T
V0
Loudness on: the increment of the loudness characteristics is linear at every volume step in the range from +20 to -11 dB +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
Gv (dB)
DATA V5 V4 V3 V2 V1 V0
Loudness characteristic is constant in a range from -11 dB to -31 dB -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -28 -29 -30 -31 -28 -29 -30 -31 -28 -29 -30 -31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Repetition of steps in a range from -28 dB to -31 dB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 4 Volume II setting (fader and balance) DATA FRR5 Gv (dB) FRL5 FFL5 FFR5 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 1995 Dec 19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 FRR4 FRL4 FFL4 FFR4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 15 FRR3 FRL3 FFL3 FFR3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 FRR2 FRL2 FFL2 FFR2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 FRR1 FRL1 FFL1 FFR1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
TEA6322T
FRR0 FRL0 FFL0 FFR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
DATA FRR5 Gv (dB) FRL5 FFL5 FFR5 -35 -36 -37 -38 -39 -40 -41 -42 -43 -44 -45 -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 mute mute mute mute mute mute mute mute 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRR4 FRL4 FFL4 FFR4 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRR3 FRL3 FFL3 FFR3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 FRR2 FRL2 FFL2 FFR2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 FRR1 FRL1 FFL1 FFR1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 FRR0 FRL0 FFL0 FFR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 5 Bass setting Gbass (dB) +15.0 +13.5 +15.0 +13.5 +15.0 +13.5 +12.0 +10.5 +9.0 +7.5 +6.0 +4.5 +3.0 +1.5 0(1) 0(2) -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 -15.0 -13.5 -15.0 note 3 note 3 note 3 notes 3 and 4 Notes 1. Recommended data word for step 0 dB. 2. Result of 1.5 dB boost and 1.5 dB attenuation. 3. The last four bass control data words mute the bass response. DATA BA4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BA3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 BA2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 BA1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
TEA6322T
BA0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
4. The last bass control and treble control data words (00000) enable the external equalizer connection.
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 6 Treble setting Gtreble (dB) +12.0 +10.5 +12.0 +10.5 +12.0 +10.5 +12.0 +10.5 +9.0 +7.5 +6.0 +4.5 +3.0 +1.5 0(1) 0(2) -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 note 3 note 3 note 3 note 3 note 3 note 3 note 3 notes 3 and 4 Notes 1. Recommended data word for step 0 dB. 2. Result of 1.5 dB boost and 1.5 dB attenuation. 3. The last eight treble control data words select treble output. DATA TR4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TR3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 TR2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 TR1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
TEA6322T
TR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
4. The last treble control and bass control data words (00000) enable the external equalizer connection.
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
Table 7 Loudness setting DATA LOFF 0 1 Selected input DATA FUNCTION SC2 Stereo inputs IAL and IAR Stereo inputs IBL and IBR Stereo inputs ICL and ICR Stereo inputs IDL and IDR (Stereo inputs) IAL and IAR Differential inputs IAL, IAR and COM No input (input mute) Mono input COM 1 1 1 1 0 0 0 0 SC1 1 1 0 0 1 1 0 0 SC0 1 0 1 0 1 0 1 0 FUNCTION Table 9 Mute mode
TEA6322T
CHARACTERISTIC With loudness Linear Table 8
DATA GMU Direct mute off Mute off delayed until the next zero crossing Direct mute Mute delayed until the next zero crossing 0 0 1 1 ZCM 0 1 0 1
1995 Dec 19
19
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
handbook, full pagewidth
18
MED423
Gbass (dB)
12
6
0
-6
-12
-18 10
10 2
10 3
f (Hz)
10 4
Fig.3 Bass control.
handbook, full pagewidth
15
MED424
Gtreble (dB)
10
5
0
-5
-10
-15 10 2
10 3
10 4
f (Hz)
10 5
Fig.4 Treble control.
1995 Dec 19
20
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
MED425
handbook,20 pagewidth full
Gv (dB) 10
0
-10
-20
-30
-40 10
10 2
10 3
10 4
f (Hz)
10 5
Fig.5 Volume control with loudness (including low roll-off frequency).
MED426
handbook, full pagewidth
100
S/N (dB) 90
(1)
(2) (3)
80
70
60
50 10 -4 (1) Vi = 2.0 V. (2) Vi = 0.5 V. (3) Vi = 0.2 V.
10 -3
10 -2
10 -1
1
Po (W)
10
Fig.6 Signal-to-noise ratio; noise weighted: CCIR468-2, quasi peak.
1995 Dec 19
21
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
MED427
handbook, full pagewidth
110
S/N (dB)
(1)
100
(2)
90
(3)
80
70
60 10 -4 (1) Unweighted RMS. (2) CCIR-468-2 RMS. (3) CCIR-468-2 quasi-peak.
10 -3
10 -2
10 -1
1
Po (W)
10
Fig.7 Signal-to-noise ratio; Vi = 2 V; Pmax = 6 W.
handbook, full pagewidth
250
MHA086
noise (V) 200
(1) (2)
150
(3) (4)
100
50
0 -70
-50
-30
-10
10
gain (dB)
30
(1) Symmetrical input; loudness on. (2) Symmetrical input; loudness off.
(3) Stereo/mono inputs; loudness on. (4) Stereo/mono inputs; loudness off.
Fig.8 Noise output voltage; CCIR468-2, quasi peak.
1995 Dec 19
22
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
handbook, full pagewidth
-60
MED429
(dB)
-80
-100
-120
-140
20
50
10 2
200
500
10 3
2 x 10 3
5 x 10 3
10 4
2 x 10 4 f (Hz)
Fig.9 Muting.
1995 Dec 19
23
Philips Semiconductors
Preliminary specification
Sound fader control circuit
If the 20 dB gain is not required for the maximum volume position, it will be an advantage to use the maximum boost gain and then increased attenuation in the last section, Volume II.
TEA6322T
Therefore the loudness will be at the correct place and a lower noise and offset voltage will be achieved.
handbook, halfpage
POWER STAGE
TEA6322T
G = 20 dB VI(min) = 200 mV P(max) = 100 W at 4
MHA087
Vo = 2 V for P(max)
a.
handbook, halfpage
POWER STAGE
TEA6322T
G = 26 dB VI(min) = 200 mV P(max) = 100 W at 4
MHA088
Vo = 1 V for P(max)
b.
a.Gain volume I = 20 dB (Gv(max)); gain volume II = 0 dB; fader and balance range = 55 dB. b.Gain volume I = 20 dB (Gv(max)); gain volume II = -6 dB global setting; fader and balance range now 49 dB, previously 55 dB.
Fig.10 Level diagram.
1995 Dec 19
24
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
handbook, full pagewidth
+
VP VCC 8.5 V inputs
20 18 16 14 17 27 25 23 21 38 5 6
+8.5 V to oscilloscope
4.7 k
470 F
TEA6322T
35 36
outputs to oscilloscope
3
4
24
26
4 x 4.7 F
9 x 220 nF 9 x 600
47 F
100 F
4 x 10 k
MHA089
Fig.11 Turn-on/off power supply circuit diagram.
handbook, full pagewidth
10
MED433
(V) 8
(1) 6
4 (2)
2
0 0 (1) VCC. (2) VO. 1 2 3 4 t (s) 5
Fig.12 Turn-on/off behaviour.
1995 Dec 19
25
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
handbook, full pagewidth
+5 V 220 nF 100 F 26 13 VCC = 8.5 V 0.1 F 10 k 1000 F 38 40 3 4 24 47 F output right output left front and rear 4.7 F VO TEA6322T 1 SDA SCL 11 9 8 7 2 33 nF 5.6 nF 4.7 k
VP
0.2 V (RMS)
600 220 nF
input A to D left and right and input mono
28
30
32
33
34
MHA090
220 nF
33 nF
5.6 nF
Fig.13 Test circuit for power supply ripple rejection (RR).
handbook, full pagewidth
+5 V 220 nF 100 F 26 13 VCC = 8.5 V 470 F 0.1 F 3 4 24 47 F input A to D right and left 220 nF Vi 600 220 nF input A to D left and right and input mono output left output right front and rear 4.7 F VO TEA6322T 1 SDA 38 40 SCL 11 9 8 7 2 33 nF 5.6 nF 4.7 k
Vp
28
30
32
33
34
MHA091
220 nF
33 nF
5.6 nF
Fig.14 Test circuit for channel separation (cs). 1995 Dec 19 26
Philips Semiconductors
Preliminary specification
Sound fader control circuit
Loudness filter calculation example Figure 15 shows the basic loudness circuit with an external low-pass filter application. R1 allows an attenuation range of 21 dB while the boost is determined by the gain stage V2. Both result in a loudness control range of +20 to -12 dB. Defining fref as the frequency where the level does not change while switching loudness on/off. The external resistor R3 for fref can be calculated as: 10 R3 = R1 -------------------- . With Gv = -21 dB and R1 = 33 k, G 1 - 10 R3 = 3.2 k is generated. For the low-pass filter characteristic the value of the external capacitor C1 can be determined by setting a specific boost for a defined frequency and referring the gain to Gv at fref as indicated above. ( R1 + R3 ) x 10 - R3 1 ------------ = ------------------------------------------------------------Gv jC 1 -----20 1 - 10 For example: 3 dB boost at f = 1 kHz Gv = Gv(ref) + 3 dB = -18 dB; f = 1 kHz and C1 = 100 nF. If a loudness characteristic with additional high frequency boost is desired, an additional high-pass section has to be included in the external filter circuit as indicated in the block diagram. A filter configuration that provides AC coupling avoids offset voltage problems.
Gv -----20 -----20
v
TEA6322T
handbook, halfpage
CKVL
0 dB 11 V1 R1 33 k 12
Gv -----20
V2
C1 R3
R2
MHA092
Fig.15 Basic loudness circuit.
1995 Dec 19
27
Philips Semiconductors
Preliminary specification
Sound fader control circuit
INTERNAL PIN CONFIGURATIONS Values shown in Figs 16 to 28 are typical DC values; VCC = 8.5 V.
TEA6322T
5 + 1 5V 1.8 k 80 4.25 V
MBE900
MHA093
Fig.16 Pin 1: SDA (I2C-bus data).
Fig.17 Pins 5, 6, 10, 31, 35, 36: output signals.
7 4.25 V + +
+
8 4.25 V
80 2.4 k
MHA094
MHA095
Fig.18 Pins 7 and 34: treble control capacitors.
Fig.19 Pins 8 and 33: bass control capacitor outputs.
1995 Dec 19
28
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
9 4.25 V 4.16 k + 11 4.25 V +
9.4 k 150 k
4.25 V 4.25 V
MHA097 MHA096
Fig.20 Pins 9 and 32: bass control capacitor inputs.
Fig.21 Pins 11 and 30: input volume 1, control part.
12 4.25 V +
+
13 4.25 V
80 1.12 k
MHA098
MHA099
Fig.22 Pins 12 and 29: input loudness, control part.
Fig.23 Pins 13 and 28: output source selector.
1995 Dec 19
29
Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6322T
2 14 4.25 V +
+
1.5 V
constant 2.2 V
35 k
4.25 V
MHA100 MHA102
Fig.24 Pins 14, 16 to 18, 20, 21, 23, 25, 27: inputs.
Fig.25 Pin 2: mute control.
+ 8.4 V 4.7 k 300 + 3.4 k 5 k 4.25 V 26 3.4 k
24
MHA101
Fig.26 Pin 24: filtering for supply; pin 26: reference voltage.
38
apply +8.5 V to this pin
40 5V 1.8 k
MHA104 MHA103
Fig.27 Pin 38: supply voltage.
Fig.28 Pin 40: SCL (I2C-bus clock).
1995 Dec 19
30
Philips Semiconductors
Preliminary specification
Sound fader control circuit
PACKAGE OUTLINE VSO40: plastic very small outline package; 40 leads
TEA6322T
SOT158-1
D
E
A X
c y HE vMA
Z 40 21
Q A2 A1 pin 1 index Lp L 1 e bp 20 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.70 0.11 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 bp 0.42 0.30 c 0.22 0.14 D (1) 15.6 15.2 E (2) 7.6 7.5 0.30 0.29 e 0.762 0.03 HE 12.3 11.8 0.48 0.46 L 2.25 Lp 1.7 1.5 Q 1.15 1.05 v 0.2 w 0.1 y 0.1 Z (1) 0.6 0.3
0.012 0.096 0.017 0.0087 0.61 0.010 0.004 0.089 0.012 0.0055 0.60
0.067 0.089 0.059
0.045 0.024 0.008 0.004 0.004 0.041 0.012
7o 0o
Notes 1. Plastic or metal protrusions of 0.4 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT158-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-24
1995 Dec 19
31
Philips Semiconductors
Preliminary specification
Sound fader control circuit
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all VSO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering techniques can be used for all VSO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end.
TEA6322T
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TEA6322T
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1995 Dec 19
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Philips Semiconductors
Preliminary specification
Sound fader control circuit
NOTES
TEA6322T
1995 Dec 19
34
Philips Semiconductors
Preliminary specification
Sound fader control circuit
NOTES
TEA6322T
1995 Dec 19
35
Philips Semiconductors - a worldwide company
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Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCD47 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513061/1100/01/pp36 Document order number: Date of release: 1995 Dec 19 9397 750 00535

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